In accordance with an error correction coding method defined by ITU-T recommendation G.975 shown in patent reference 1, a transmit side converts a transmission information sequence inputted thereto in series order into 128 parallel information sequences using an FEC (Forward Error Correction) demultiplexing circuit. It can be considered that this conversion is interleaving processing having a depth of 128. An overhead is added to the 128 parallel information sequences, and a speed conversion corresponding to an FEC parity part is then performed on them.
After that, they are coded in units of 8 parallels high and 239 times width with RS (Reed Solomon) codes. This coding processing is carried out in such a manner that 16 coding processes are done in parallel, and a coded sequence having a 255-time width is generated. This whole code word sequence of 128 parallels high and 255 times width is one unit, and is called an FEC frame.
Each FEC frame of 128 parallels high is converted into a code word sequence which will be outputted and transmitted by an FEC multiplexing circuit in series order after RS coded. It can be considered that this conversion is deinterleaving processing having a depth of 128.
A receive side converts a received sequence arranged in series order into which noise has been mixed when passing through an optical communication path into 128 parallel received sequences using an FEC demultiplexing circuit having the same structure as that of the transmit side. The receive side then performs RS code decoding processing on the 128 parallel received sequences in units of 8 parallels high and 239 times width. The receive side further delivers the RS-decoded 128 parallel sequences to a speed conversion unit and an overhead separating circuit so as to convert them into 128 parallel estimated information sequences. The receive side then converts the sequences into estimated information sequences to be outputted in series order using an FEC multiplexing circuit having the same structure as that of the transmit side.
In accordance with the technology disclosed in patent reference 1, the order of inputted information is rearranged using a first interleaving circuit, a first error correcting code is generated using an RS(239,223) coding circuit, the order of the information is rearranged into the original one using a first deinterleaving circuit, and a second error correcting code is generated using an RS(255,239) coding circuit. At the time of decoding the information, the second error correcting code is decoded and errors included in the information are corrected using an RS(255,239) decoding circuit, the order of the information is rearranged using a second interleaving circuit, the first error correcting code is decoded and remaining errors included in the information is corrected using an RS(239,223) decoding circuit, and the order of the information is rearranged into the original one using a second deinterleaving circuit.
[Patent reference 1] JP, 2001-168734, A
A problem with the prior art error correction coding apparatus constructed as mentioned above is that because it is necessary to perform coding processing and transmission processing in units of FEC frames, and each of the processings is restricted by the size of FEC frames, the capability of correcting for burst errors is restricted by the size of FEC frames.
The present invention is made in order to solve the above-mentioned problem, and it is therefore an object of the present invention to provide an improvement in the capability of correcting for burst errors without being restricted by the size of FEC frames, i.e., units on which coding processing is performed.